With development in the semiconductor technologies, sizes of semiconductor devices are continually scaling down, while integration level of integrated circuits becomes more and more intensive, thus the process for manufacturing semiconductor device structures faces increasingly strict requirements. In the formation process of gate electrodes, as the pitch between devices becomes increasingly narrow, particularly in the 45 nm or below technology, the process for etching gate electrodes already stands out to be a significant issue which requires semiconductor manufacturing industry to make common effort.
In the prior art, gate electrodes are usually etched by means of a double-mask lithography technology. FIG. 1a and FIG. 1b illustrate a method in the prior art for forming gate electrodes. In the figures, 100 denotes an active region formed on a semiconductor substrate. Specifically, it is preferred to form a gate electrode material layer over the whole semiconductor substrate on which the active region has already been formed and other necessary processes have been performed, then to coat the gate electrode material layer with photo-resist, to pattern the photo-resist into the shape of gate electrode lines to be formed, and then to etch the gate electrode material layer with the patterned photo-resist serving as a mask so as to form gate electrode lines 200 shown in FIG. 1a, and then to perform lithography with use of a second mask plate so as to form gate electrode line cuts 300 shown in FIG. 1b by etching. In subsequent processes, it is necessary to form sidewall spacers outside the gate electrodes, by which the gate electrode line cuts 300 are completely filled by the insulating material of the sidewall spacers, so that the gate electrodes are electrically isolated.
However, in aforesaid process, the cuts formed between the gate electrodes at the second-time lithography and etching are very small, making them hard to be filled with an insulating material when sidewall spacers are formed, which consequently is prone to cause a short circuit between gate electrodes in subsequent processes (e.g. such as ion implantation).
Additionally, since aforesaid lithography technology requires extremely high preciseness, Optical Proximity Correction (OPC) becomes very difficult. In the process of 45 nm or below, this method cannot satisfy the requirements of preciseness in gate mask imaging and etching.
Therefore, it is necessary to propose a more advanced gate electrode formation technology to solve abovementioned problems.